Index
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Index
Acquire semantics
Acquire Semantics
Altix system addresses
Itanium 2 Processors and Altix System Addresses
Architectural considerations
Special Architectural Considerations
Bus addresses
Bus Addresses - PCI/PCI-X Buses
Device driver interrupt registration
Device Driver Interrupt Registration - IRQs
Direct memory access
Direct Memory Access
device interrupts and posted DMAs
Device Interrupts and Posted DMAs
PIO reads and posted DMAs
PIO Reads and Posted DMAs
Polling memory for completion and posted DMA data
Polling Memory for Completion and Posted DMA Data
Direct memory access addresses (DMA)
Direct Memory Access Addresses (DMA)
DMA mapping interfaces
Polling Memory for Completion and Posted DMA Data
Legacy functionality
Legacy Functionality
Memory
fencing
Memory Fencing
ordering
Memory Ordering
PIO write flush macros
Posted PIO
write
Calls
posted PIO write calls
Posted PIO
write
Calls
Programmable IO read/write addresses
Programmable IO Read/Write Addresses
Release semantics
Release Semantics
System physical memory addresses
System Physical Memory Addresses
Write operations
Programmable I/O Write Operations